KERALA UNIVERSITY Class 8 computer system architecture Question Paper 2019

Practice authentic previous year questions for better exam preparation.

Sample Questions

What is the need for cache coherence mechanisms?
Briefly describe cache coherence problems.
Differentiate implicit and explicit parallelism.
(b) Define (i) speedup (ii) efficiency (iii) throughput of a processor pipline.
(a) Consider the following reservation table for four stage pipeline with clock cycle $=20 \mathrm{~ns}$.